Tools: Yosys 0.70+201 (git 0ad867ab5, with its bundled ABC), Icarus Verilog 14.0 (devel), OpenSTA 2.5.0, Python 3.12, the SKY130 PDK (sky130A, installed with ciel). Every number in results/ and in the reports comes from one clean run on these versions (Ubuntu 24.04 under WSL2).

export PDK_ROOT=~/.ciel   # where ciel installed sky130A
make setup     # < 1 min: links given/ (student pack) and pdk/ (PDK_ROOT/sky130A)
make check     # < 1 min: Yosys, ABC, Icarus, OpenSTA, the PDK files, the two given libraries
make test      # < 1 min: unit tests, Table 4 self-test, and every broken case
make all       # ~ 13 min: the whole flow, steps 1 to 12 of handout section 4
make demo IN=<design.v or name>   # ~ 1 min: the whole flow on one design (interview demo)

OpenSTA without root: conda create -p ~/eda-sta -c litex-hub -c conda-forge openroad provides ~/eda-sta/bin/sta, which the flow finds (or set STA_BIN). Without OpenSTA, make all still runs and leaves the delay table unmeasured. results/curve.png needs matplotlib in the Python that runs the flow (make all PYTHON=/usr/bin/python3 when OSS CAD Suite's own Python comes first on PATH).